The present invention relates to a method for producing a semiconductor device having good electrical properties and also to a method for forming a thin film transistor (TFT) with good electrical properties.
Among thin film semiconductor elements, the TFT is well known. TFT is composed of an insulating substrate such as glass substrate and a thin film semiconductor (usually silicon semiconductor) as an active layer formed thereon which is several hundreds to several thousands of angstroms in thickness. TFT is applied to an electro-optical device such as a liquid crystal display device and an image sensor. Picture elements and peripheral drivers are formed by TFT formed directly on a glass substrate.
In using a glass substrate, the thin film silicon semiconductor formed on the substrate has amorphous or crystalline. A structure having crystalline represents the polycrystal structure, microcrystal structure, or a mixture of amorphous and crystalline structures. TFT based on an amorphous semiconductor is slightly poor in operating speed and electrical properties, and limits its application. By contrast, TFT based on a crystalline silicon film is capable of high speed operation and has good electrical properties.
TFT based on a crystalline silicon film has a problem associated with off state current. When a negative voltage is applied to the gate electrode in an N-channel type TFT, a current does not flow between a source and a drain in principle. This is because, by applying the negative voltage, a channel becomes a P-type and therefore a PN-junction is formed between the source and the drain. In actual, the crystalline silicon film contains crystal grain boundaries, crystal defects, and dangling bonds, so that a large number of levels produce. Accordingly, charges move in the reverse direction of PN-junction through these levels. When an electric field is concentrated at the PN-junction, a current leaks in the reverse direction through the defects and traps. As a result, an off current flows between the source and the drain by applying the negative voltage to the gate electrode.
A method to solve this problem is to form a lightly doped drain (LDD) region (lightly N-type), as an electric field relaxation region, between a channel (I-type) and a drain (N-type), which prevents the concentration of electric field between them.
Another method to obtain the same effect as the LDD region is to form an offset gate region which avoids the concentration of electric field between a channel and a drain. The offset gate region is a region which does not function as the drain between the channel and the drain.
As mentioned above, an off current of TFT decreases by defects and traps in the film. Also, defects and traps retard the movement of carriers in the film and therefore prevent the operation of TFT.
On the other hand, interface properties between a channel and a gate insulating film in TFT are extremely important. The interface properties greatly affect characteristics of TFT, and are evaluated in terms of interface level. The interface level produces by defects and dangling bonds. To obtain TFT having good characteristics, it is necessary to lower the interface level at the interface between the channel and the gate insulating film.